Chemical mechanical planarisation (CMP), often called chemical mechanical polishing, is a procedure to level thin layers. CMP was originally developed for use with typical semiconductor materials but is also being increasingly used in manufacturing micro systems. CMP is essential for low-K materials and in the manufacture of sensitive wafers whose surface consists of two materials made from one material compound, for example. Due to the different hardnesses and electricity of both materials, purely mechanical processing in this case would lead to notches in the material transition areas.
SiC becomes more and more established in the industry and is considered to be the future of power electronics.
The benefits of SiC against Si for products like Schottky barrier diodes or FETs/MOSFETs in converter, inverter, power supplies, battery chargers and motor control systems are diverse and based on better material properties, wider bandgap, more temperature stability, lower switching losses, higher frequency operation and intrinsic body diode.
Our long experience with hard material helps us to understand the demands from our customer to develop the right SiC CMP technology to increase chip performance and power efficiency.
SiC wafer surface quality is critically important to SiC device fabrication as any defects on the surface of the wafer will migrate through the subsequent layers. To produce uniform wafers with the highest quality surfaces our CMP tool offers the highest quality for your demand. Options for higher removal rate and single-side or front & backside polishing as dry-in-dry-out cleaning, measurement of material removal with our CMP system for customer highest process success are available.